// +FHDR----------------------------------------------------------
// Copyright (c) 2023, RJMicro Technology Co.,Ltd.
// RJMicro Confidential Proprietary
// ---------------------------------------------------------------
// FILE NAME       : .v
// DEPARTMENT      : IC Dept
// AUTHOR          :
// AUTHOR'S EMAIL  :
// ---------------------------------------------------------------
//
// Description     :
// 12'h000  LINCR1
// 12'h004  LINIER
// 12'h008  LINSR
// 12'h00C  LINESR
// 12'h010  UARTCR
// 12'h014  UARTSR
// 12'h018  LINTCSR
// 12'h01C  LINOCR
// 12'h020  LINTOCR
// 12'h024  LINFBRR
// 12'h028  LINIBRR
// 12'h02C  LINCFR
// 12'h030  LINCR2
// 12'h034  BIDR
// 12'h038  BDRL
// 12'h03C  BDRM
// 12'h040  IFER
// 12'h044  IFMI
// 12'h048  IFMR
// 12'h04C  IFCR[%S]
// 12'h08C  GCR
// 12'h090  UARTPTO
// 12'h094  UARTCTO
// 12'h100  LINOUTPHY
// 12'h104  LININPHY
// 12'h108  LINSWITCH
// 12'h10C  LINTESTMODE
// 12'h110  LINPHYCFG
// 12'h114  LINPHYIE
// 12'h118  LINPHYSR
// 12'h11C  LINPHYCLR
// 12'h120  LINPHYMTOCNT
// 12'h124  LINPHYSTOCNT
// -FHDR
// ---------------------------------------------------------------

module lin_regfile (
    input                  pclk                ,
    input                  prstn               ,

    input                  psel                ,
    input  [11:0]          paddr               ,
    input                  penable             ,
    input                  pwrite              ,
    input  [31:0]          pwdata              ,
//    output                pready              ,
//    output                pslverr             ,
    output [31:0]          prdata
);

// ------------------------------------------------------------
// APB write read enable
// ------------------------------------------------------------
reg     [31:0]  ff_rdata;
wire            read_en   = psel && (~penable) && (~pwrite);
wire            write_en  = psel && (~penable) && pwrite;
wire    [11:0]  addr      = paddr;
wire    [31:0]  wdata     = pwdata;

always @(posedge pclk or negedge prst) begin
    if (!prst)
        prdata <= 32'b0;
    else if (read_en) 
        prdata <= ff_rdata[31:0];
end

// ------------------------------------------------------------
// Internal Signals
// ------------------------------------------------------------


// ------------------------------------------------------------
// write_process
// ------------------------------------------------------------


// ------------------------------------------------------------
// read_process
// ------------------------------------------------------------


always @ (*) begin
    ff_rdata = 32'h0;
    if (read_en) begin
        case (addr[11:2])
            default: ff_rdata = 32'h0;
        endcase
    end
end
// ------------------------------------------------------------
// Assign
// ------------------------------------------------------------
// ------------------------------------------------------------
// End of the module
// ------------------------------------------------------------
endmodule
